This ADC consists of
Counter, a DAC, an Analog comparator and a control AND gate comparator serves
as the active LOW end of conversion signal EOC.
WORKING:
A state pulse is applied
to reset the counter to zero.when start pulse is HIGH it inhibit the clock to
pass into the counter as it passed with
AND gate with start pulse.
When input contains all 0
then DAC’s output Vi=0.
Since V1 > Vi,
therefore comparator output EOC (active low signal)will be high
When start becomes LOW
AND gate is enabled which allows the clock pulses to pass through the counter
As counter advances DAC output,
Vi increases one step at a time.
This continues until Vi
reaches to a step that exceeds V1 by amount equal to or greater than threshold voltage
Vd. At this point, EOC (ALS) will go LOW and inhibit flow of pulses into the counter
and it will stop counting.
Now, conversion process
is complete as signaled by the HIGH to LOW transition at EOC, and contents of
counter are digital representation ofV1
The counter will hold
this digital value until next Start pulse initiates a new conversion.
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