V3 Technologies Conducting IPT in Tanjore

V3 Technologies Tanjore conducting In Plant training for Engineering pursuing students.

Students belonging to ECE, CSE, EEE & IT can join.
Entire session will be purely practical .

IPT & Course include 

• Embedded 
• MATLAB
• PCB Design
• LABVIEW Robotics
• Basic Electronics C & C++
• Wireless Network
• WSN
• VLSI 

For further details contact 

V3 Technologies
No 271, SS Towers,
R.R. Nagar
(Near Bombay Sweets)
Thanjavur-5.

Cell : 8870525672
Phone : 04362 - 228230
Google + : https://plus.google.com/116234348028795157376/about?gl=in&hl=en

For direction help click the link below

How to reach us from Tanjore New Bus stand

Single Slope ADC

Major advantage is it does not require D/A converter and also it does not require any precision device.. such as  DAC or VCO. It uses linear ramp generator to produce a constant slope reference voltage

Working:

             Initially counter is reset and ramp generator output is 0, which makes the input voltage greater than the reference voltage and produce a high output from the comparator. This high output of comparator enables the clock to the counter and starts the ramp generator.

Ramp output will increase until it equals the analog input V1 at this point, ramp is reset and binary count is stored in the latches by control logic.

Successive approximation ADC

Working method everything is similar to RAMP type ADC.Here it have fixed value of conversion time regardless the value of analog input.

And a small variation is it does not use counter to provide input to DAC block instead it use register.The control logic modifies content of the register bit until register data are digital equivalent of the analog inputV1.

Advantages:

                     Total conversions time for N bit SAC is N clock.

Continuation of ADC - DIGITAL RAMP A/D CONVERTER

This ADC consists of Counter, a DAC, an Analog comparator and a control AND gate comparator serves as the active LOW end of conversion signal EOC.

  

WORKING:

    

A state pulse is applied to reset the counter to zero.when start pulse is HIGH it inhibit the clock to pass into the counter as  it passed with AND gate with start pulse.

When input contains all 0 then DAC’s output Vi=0.

Since V1 > Vi, therefore comparator output EOC (active low signal)will be high

When start becomes LOW AND gate is enabled which allows the clock pulses to pass through the counter

As counter advances DAC output, Vi increases one step at a time.

This continues until Vi reaches to a step that exceeds V1 by amount equal to or greater than threshold voltage Vd. At this point, EOC (ALS) will go LOW and inhibit flow of pulses into the counter and it will stop counting.

Now, conversion process is complete as signaled by the HIGH to LOW transition at EOC, and contents of counter are digital representation ofV1

The counter will hold this digital value until next Start pulse initiates a new conversion.